1. Field of the Invention
This invention relates to a non-volatile semiconductor memory device (EEPROM).
2. Description of Related Art
A NAND-type flash memory is well known as one of electrically!erasable and programmable ROMs (EEPROMs). The NAND-type flash memory has a page buffer, which is able to read and write 1-page data, and data read and write are performed by a page. In case it is required to over-write data into a block, a write sequence is controlled as to write data by a page after having erased the block. Therefore, if it is required to rewrite part of block data, it is necessary to do a page copy operation in such a manner as to read out data of the block, and then write it into another block (i.e., spare block) which has already been erased.
To transfer data between blocks, it is necessary for performing multiple data read and write operations. This leads to data disturbance. Therefore, to assure of data reliability in a page copy mode, it is desirable to do error checking and correcting for the read out data of the respective copy source pages. In case an ECC circuit is disposed outside the memory chip, the read out data, which is read out of the cell array and stored in the page buffer, is output outside of the chip and input to the ECC circuit. Usually, data outputting from the page buffer to I/O terminals is performed in such a manner that one page data is serially transferred by a byte. Write data, an error bit of which is corrected in the ECC circuit, is written into a copy destination page. In this case, the write data loading may be done as to rewrite part of the read data held in the page buffer, which includes an error bit (for example, refer to Japanese Patent application Laid Open No. 2003-030993).
The above-described page copy operation will be performed without making so much the sacrifice of performance due to ECC, in case it is performed within a cell array which is to be connected to a page buffer. However, there is a problem in case page copy is performed between cell array planes in a flash memory having a plurality of cell array planes. For example, assume here that one page in one plane is formed of 2 kByte normal data area and 64 Byte redundant area, and assume that it takes 50 nsec for loading 1-Byte data. In case of copy operation within a plane, it takes only 50 nsec to load 1-Byte data including an error-corrected bit. By contrast, to do a copy operation between planes, it is required to load one page data. In detail, one page data read out of a plane, which is partially corrected in case an error bit has been detected, while without correcting in case no errors have been detected, should be loaded in another page buffer connected to another plane. Therefore, it takes a time of 50 [nsec]×2112[Byte] (i.e., longer than 100 [μsec]) for loading data.
If a specification is defined as to restrict a page copy operation between different planes in a flash memory with plural planes for preventing the above-described sacrifice of performance, the memory will become incompatible with other flash memories with only one plane. Such the flash memory becomes hard to deal with for users.